Rainbow Electronics DS31256 - Manual (Page 130)

DS31256
130 of 181
10. PCI BUS
10.1 General Description of Operation
The PCI block interfaces the DMA block to an external high-speed bus. The PCI block complies with
Revision 2.1 (June 1, 1995) of the PCI Local Bus Specification. HDLC packet data always passes to and
from the Envoy through the PCI bus. The user has the option to configure and monitor the internal
device registers either through the PCI bus (local bus bridge mode) or through the local bus (local bus
configuration mode). When the local bus bridge mode is used, the host on the PCI bus can also bridge to
the local bus and sets/monitors the PCI configuration registers. When the local bus configuration mode is
used, the CPU on the local bus sets/monitors the PCI configuration registers.
The PCI configuration registers (
Figure 10-1 ) are described in detail in Section 10.2 . The following notes
apply to the PCI configuration registers:
1) All unused locations (the shaded areas of Figure 10-1 ) return 0s when read.
2) Read-only locations can be written with either 1 or 0 with no effect.
3) All bits are read/write, unless otherwise noted.
Figure 10-1. PCI Configuration Memory Map
0x000
0x004
0x008
0x00C
0x010
0x03C
0x100
0x104
0x108
0x10C
0x110
Device ID Vendor ID
Status Command
Class Code Revision ID
Header Type Latency Timer
Base Address for Device Configuration 0x000
Max. Latency Min. Grant Interrupt Pin Interrupt Line
Header Type
Device ID Vendor ID
Status Command
Class Code Revision ID
0x00000 Base Address for Local Bus
Cache Line Size
Interrupt Pin Interrupt Line 0x13C