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Pci target abort, Figure 10-8. pci target abort, 7 pci target abort – Rainbow Electronics DS31256 User Manual

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10.1.7 PCI

Target

Abort

Targets can also abort the current transaction, which means they do not wish for the initiator to attempt
the request again. No data is transferred in a target abort scenario. A target abort is signaled to the
initiator by the simultaneous assertion of PSTOP and deassertion of PDEVSEL (

Figure 10-8

). When the

Envoy is a target, it only issues a target abort when the host is accessing the local bus. This occurs when
the host attempts a bus transaction with a combination of byte enables (PCBE) that are not supported by
the local bus. If such a scenario occurs, it reports through the target-abort-initiated status bit in the PCI
command/status configuration register (Section

10.2

). See Section

11.1

for details about local bus

operation. When the Envoy is a bus master, if it detects a target abort, it reports through the target abort
detected by master status bit in the PCI command/status configuration register (Section

10.2

).

Figure 10-8. PCI Target Abort

1

2

3

4

5

6

7

8

9

10

PCLK

PFRAME

PSTOP

PDEVSEL

PTRDY