Rainbow Electronics DS31256 - Manual (Page 141)

DS31256
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Register Name: PDCM
Register Description: PCI Device Configuration Memory Base Address Register
Register Address:
0x010h
LSB
Base Address (Read Only/Set to 0h) PF TYPE1 TYPE0 MSI
Base Address Base Address (Read Only/Set to 0h)
Base Address
MSB
Base Address
Note: Read-only bits in the PDCM register are underlined; all other bits are read-write.
Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the internal device
configuration registers are mapped to memory space.
Bits 1, 2/Type 0, Type 1. These read-only bits are forced to 00b to indicate that the internal device configuration
registers can be mapped anywhere in the 32-bit address space.
Bit 3/Prefetchable (PF). This read-only bit is forced to 0 to indicate that prefetching is not supported by the
device for the internal device configuration registers.
Bits 4 to 11/Base Address. These read-only bits are forced to 0 to indicate that the internal device configuration
registers require 4kB of memory space.
Bits 12 to 31/Base Address. These read/write bits define the location of the 4k memory space that is mapped to
the internal configuration registers. These bits correspond to the most significant bits of the PCI address space.
Register Name:
PINTL0
Register Description: PCI Interrupt Line and Pin/Minimum Grant/Maximum Latency Register 0
Register Address:
0x03Ch
LSB
Interrupt Line
Interrupt Pin (Read Only/Set to 01h)
Maximum Grant (Read Only/Set to 05h)
MSB
Maximum Latency (Read Only/Set to 0 Fh)
Bits 0 to 7/Interrupt Line. These read/write bits indicate and store interrupt line routing information. The device
does not use this information, it is only posted here for the host to use.
Bits 8 to 15/Interrupt Pin. These read-only bits are forced to 01h to indicate that PINTA is used as an interrupt.
Bits 16 to 23/Minimum Grant. These read-only bits are used to indicate to the host how long of a burst period
the device needs, assuming a clock rate of 33MHz. The values placed in these bits specify a period of time in
0.25
ms increments. These bits are forced to 05h.
Bits 24 to 31/Maximum Latency. These read-only bits are used to indicate to the host how often the device needs
to gain access to the PCI bus. The values placed in these bits specify a period of time in 0.25
ms increments. These
bits are forced to 0Fh.