Rainbow Electronics DS31256 - Manual (Page 156)

DS31256
156 of 181
Figure 11-6. 16-Bit Write Cycle
Intel Mode (LIM = 0)
Arbitration Enabled (LARBE = 1)
Bus Transaction Time = 4 LCLK (LRDY = 0100)
An attempted access by the host causes the local bus to request the bus. If bus access has not been granted
(LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once
LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has
already been granted (LBGACK asserted), the timing shown at the bottom of the page applies.
LCLK
LHOLD
LHLDA
LBGACK
32 to 1,048,576 LCLKs
LA[19:0]
LD[7:0]
LD[15:8]
LRD
LWR
Address Valid
LBHE
Data Valid
Data Valid
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
LCLK
1 2 3 4
Note: LA, LD, LBHE, LWR, and LRD are three-stated.