Rainbow Electronics DS31256 - Manual (Page 158)

DS31256
158 of 181
Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle
Intel Mode (LIM = 0)
Arbitration Disabled (LARBE = 0)
Bus Transaction Time = Timed from LRDY (LRDY = 0000)
LCLK
LA[19:0]
LD[7:0]
LD[15:8]
LWR
LRD
Address Valid
LBHE
LRDY
Data Valid
1 2 3 4 5 6 7 8 9 10
Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the
LBE status bit is set.