Rainbow Electronics DS31256 - Manual (Page 61)

DS31256
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6.6 BERT Register Description
Figure 6-8. BERT Register Set
BERTC0: BERT Control 0 LSB
n/a TINV RINV PS2 PS1 PS0 LC RESYNC
MSB
IESYNC IEBED IEOF n/a RPL3 RPL2 RPL1 RPL0
BERTC1: BERT Control 1
LSB
EIB2 EIB1 EIB0 SBE n/a n/a n/a TC
MSB
Alternating Word Count
BERTRP0: BERT Repetitive Pattern Set 0 (lower word)
LSB
BERT Repetitive Pattern Set (lower byte)
MSB
BERT Repetitive Pattern Set
BERTRP1: BERT Repetitive Pattern Set 1 (upper word)
LSB
BERT Repetitive Pattern Set
MSB
BERT Repetitive Pattern Set (upper byte)
BERTBC0: BERT Bit Counter 0 (lower word)
LSB
BERT 32-Bit Bit Counter (lower byte)
MSB
BERT 32-Bit Bit Counter
BERTBC1: BERT Bit Counter 0 (upper word)
LSB
BERT 32-Bit Bit Counter
MSB
BERT 32-Bit Bit Counter (upper byte)
BERTEC0: BERT Error Counter 0/Status
LSB
n/a RA1 RA0 RLOS BED BBCO BECO SYNC
MSB
BERT 24-Bit Error Counter (lower byte)
BERTEC1: BERT Error Counter 1 (upper word)
LSB
BERT 24-Bit Error Counter
MSB
BERT 24-Bit Error Counter (upper byte)