Rainbow Electronics DS31256 - Manual (Page 23)

DS31256
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Signal Name: PCBE0/PCBE1/PCBE2/PCBE3
Signal Description: PCI Bus Command and Byte Enable
Signal Type: Input/Output (three-state capable)
Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals
define the bus command. During the data phase, these signals are used as bus enables. During data phases, PCBE0
refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is high, the associated byte is invalid;
when low, the associated byte is valid. When the device is an initiator, this signal is an output and is updated on
the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the rising edge of
PCLK. When the device is not involved in a bus transaction, these signals are three-stated.
Signal Name:
PPAR
Signal Description: PCI Bus Parity
Signal Type: Input/Output (three-state capable)
This signal provides information on even parity across both the PAD address/data bus and the PCBE bus
command/byte enable bus. When the device is an initiator, this signal is an output for writes and an input for reads.
It is updated on the rising edge of PCLK. When the device is a target, this signal is an input for writes and an
output for reads. It is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PPAR is three-stated.
Signal Name:
PFRAME
Signal Description: PCI Cycle Frame
Signal Type: Input/Output (three-state capable)
This active-low signal is created by the bus initiator and is used to indicate the beginning and duration of a bus
transaction. PFRAME is asserted by the initiator during the first clock cycle of a bus transaction and remains
asserted until the last data phase of a bus transaction. When the device is an initiator, this signal is an output and is
updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the
rising edge of PCLK. When the device is not involved in a bus transaction, PFRAME is three-stated.
Signal Name: PIRDY
Signal Description: PCI Initiator Ready
Signal Type: Input/Output (three-state capable)
The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the PTRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction, PIRDY is deasserted when the initiator cannot
temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output
and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on
the rising edge of PCLK. When the device is not involved in a bus transaction, PIRDY is three-stated.
Signal Name: PTRDY
Signal Description: PCI Target Ready
Signal Type: Input/Output (three-state capable)
The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the PIRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction, PTRDY is deasserted when the target cannot
temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output
and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled
on the rising edge of PCLK. When the device is not involved in a bus transaction, PTRDY is three-stated.
Signal Name: PSTOP
Signal Description: PCI Stop
Signal Type: Input/Output (three-state capable)
The target creates this active-low signal to signal the initiator to stop the current bus transaction. When the device
is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator, this