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Figure 6-1. layer 1 block diagram, Figure 6-1, Shows the – Rainbow Electronics DS31256 User Manual

Page 46

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DS31256

46 of 181

Figure 6-1. Layer 1 Block Diagram











































RS

RC

RD

SLOW
HDLC

(One
per
Port)

FAST
HDLC

Layer One
State Machine

Receive

Transmit

Channel-
ized
Local
Loop-
Back
(CLLB)

Channel-
ized
Network
Loop-
Back
(CNLB)

V.54
Detector

PORT
RAM
(see
Sec.
5.3)

Invert
Clock /
Data /
Sync

Local
Loop-
Back
(LLB)

Invert
Clock /
Data /
Sync

Force
All
Ones

TC

TD

TS

Over-
Sample
with
PCLK

Un-
Channel-
ized
Network
Loopback
(UNLB)

Over-
Sample
with
PCLK

BERT/
Fast
HDLC
Mux

BERT Mux

(see Figure 5.5A)

1 of 16

LLB

UNLB

Port
0 & 1
Only

To /

From

FIFO

Block

l1_bd

Ports 0 & 1 Only

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