Rainbow Electronics DS31256 - Manual (Page 24)

DS31256
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signal is an input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PSTOP is three-stated.
Signal Name: PIDSEL
Signal Description: PCI Initialization Device Select
Signal Type: Input
This input signal is used as a chip select during configuration read and write transactions. This signal is disabled
when the local bus is set in configuration mode (LMS = 1). When PIDSEL is set high during the address phase
of a bus transaction and the bus command signals (PCBE0 to PCBE3) indicate a register read or write, the device
allows access to the PCI configuration registers, and the PDEVSEL signal is asserted during the PCLK cycle.
PIDSEL is sampled on the rising edge of PCLK.
Signal Name: PDEVSEL
Signal Description: PCI Device Select
Signal Type: Input/Output (three-state capable)
The target creates this active-low signal when it has decoded the address sent to it by the initiator as its own to
indicate that the address is valid. If the device is an initiator and does not see this signal asserted within six PCLK
cycles, the bus transaction is aborted and the PCI host is alerted. When the device is a target, this signal is an
output and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is
sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PDEVSEL is three-
stated.
Signal Name:
PREQ
Signal Description: PCI Bus Request
Signal Type: Output (three-state capable)
The initiator asserts this active-low signal to request that the PCI bus arbiter allow it access to the bus. PREQ is
updated on the rising edge of PCLK.
Signal Name: PGNT
Signal Description: PCI Bus Grant
Signal Type: Input
The PCI bus arbiter asserts this active-low signal to indicate to the PCI requesting agent that access to the PCI bus
has been granted. The device samples PGNT on the rising edge of PCLK and, if detected, initiates a bus
transaction when it has sensed that the PFRAME signal has been deasserted.
Signal Name: PPERR
Signal Description: PCI Parity Error
Signal Type: Input/Output (three-state capable)
This active-low signal reports parity errors. PPERR can be enabled and disabled through the PCI configuration
registers. This signal is updated on the rising edge of PCLK.
Signal Name: PSERR
Signal Description: PCI System Error
Signal Type: Output (open drain)
This active-low signal reports any parity errors that occur during the address phase. PSERR can be enabled and
disabled through the PCI configuration registers. This signal is updated on the rising edge of PCLK.
Signal Name: PINTA
Signal Description: PCI Interrupt
Signal Type: Output (open drain)
This active-low (open drain) signal is asserted low asynchronously when the device is requesting attention from
the device driver. PINTA is deasserted when the device-interrupting source has been serviced or masked. This
signal is updated on the rising edge of PCLK.