Rainbow Electronics DS31256 - Manual (Page 95)

DS31256
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Status/Interrupts
On each read of the free queue by the DMA, the DMA sets either the status bit for receive DMA large
buffer read (RLBR) or the status bit for receive DMA small buffer read (RSBR) in the status register for
DMA (SDMA). The DMA also checks the receive free-queue large-buffer host write pointer and the
receive free-queue small-buffer host write pointer to ensure that an underflow does not occur. If it does
occur, the DMA sets either the status bit for receive DMA large buffer read error (RLBRE) or the status
bit for receive DMA small buffer read error (RSBRE) in the status register for DMA (SDMA), and it
does not read the free queue nor does it increment the read pointer. In such a scenario, the receive FIFO
can overflow if the host does not provide free-queue descriptors. Each of the status bits can also (if
enabled) cause an hardware interrupt to occur. See Section
5 for more details.
Free-Queue Burst Reading
The DMA has the ability to read the free queue in bursts, which allows for a more efficient use of the
PCI bus. The DMA can grab messages from the free queue in groups rather than one at a time, freeing up
the PCI bus for more time-critical functions.
An internal FIFO stores up to 16 free-queue descriptors (32 dwords, as each descriptor occupies two
dwords). The free queue can either opeate in dual or singular circular queue mode. It can be divided into
large buffer and small buffer. The LBSA (large buffer starting address) and the LBEA (large buffer
ending address) form the large buffer queue, and the SBSA (small buffer starting address) and the
RFQEA (receive free-queue end address) form the small buffer queue. When the SBSA is not equal to
and greater than the RFQEA, the free queue is set up in a dual circular mode. If the SBSA is equal to the
FRQEA, the free queue is operating in a single queue mode. When the free queue is operated as a dual
circular queue supporting both large and small buffers, then the FIFO is cut into two 8-message FIFOs. If
the free queue is operated as a single circular queu supporting only the large buffers, then the FIFO is set
up as a single 16-descriptor FIFO. The host must configure the free-queue FIFO for proper operation
through the receive DMA queues control (RDMAQ) register (see the following).
When enabled through the receive free-queue FIFO-enable (RFQFE) bit, the free-queue FIFO does not
read the free queue until it reaches the low watermark. When the FIFO reaches the low watermark
(which is two descriptors in the dual mode or four descriptors in the single mode), it attempts to fill the
FIFO with additional descriptors by burst reading the free queue. Before it reads the free queue, it checks
(by examining the receive free-queue host write pointer) to ensure the free queue contains enough
descriptors to fill the free-queue FIFO. If the free queue does not have enough descriptors to fill the
FIFO, it only reads enough to keep from underflowing the free queue. If the FIFO detects that there are
no free-queue descriptors available for it to read, then it sets either the status bit for the receive DMA
large buffer read error (RLBRE) or the status bit for the receive DMA small buffer read error (RSBRE)
in the status register for DMA (SDMA); it does not read the free queue nor does it increment the read
pointer. In such a scenario, the receive FIFO can overflow if the host does not provide free-queue
descriptors. If the free-queue FIFO can read descriptors from the free queue, it burst reads them,
increments the read pointer, and sets either the status bit for receive DMA large buffer read (RLBR) or
the status bit for the receive DMA small buffer read (RSBR) in the status register for DMA (SDMA).
See Section
5 for more details on status bits.