Rainbow Electronics DS31256 - Manual (Page 22)

DS31256
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Signal Name: JTDI
Signal Description: JTAG IEEE 1149.1 Test Serial-Data Input
Signal Type: Input (with internal 10kΩ pullup)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If unused, this signal should be
pulled high. This signal has an internal pullup.
Signal Name: JTDO
Signal Description: JTAG IEEE 1149.1 Test Serial-Data Output
Signal Type: Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If unused, this signal should be left
open circuited.
Signal Name:
JTRST
Signal Description: JTAG IEEE 1149.1 Test Reset
Signal Type: Input (with internal 10kΩ pullup)
This signal is used to synchronously reset the test access port controller. At power-up, JTRST must be set low and
then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation. If
boundary scan is not used, this signal should be held low. This signal has an internal pullup.
Signal Name: JTMS
Signal Description: JTAG IEEE 1149.1 Test Mode Select
Signal Type: Input (with internal 10kΩ pullup)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE
1149.1 states. If unused, this signal should be pulled high. This signal has an internal pullup.
3.5 PCI Bus Signal Description
Signal Name: PCLK
Signal Description: PCI and System Clock
Signal Type: Input (Schmitt triggered)
This clock input provides timing for the PCI bus and the device’s internal logic. A 25MHz to 33MHz clock with a
nominal 50% duty cycle should be applied here.
Signal Name:
PRST
Signal Description: PCI Reset
Signal Type: Input
This active-low input is used to force an asynchronous reset to both the PCI bus and the device’s internal logic.
When forced low, this input forces all the internal logic of the device into its default state, forces the PCI outputs
into three-state, and forces the TD[15:0] output port-data signals high.
Signal Name:
PAD0 to PAD31
Signal Description: PCI Address and Data Multiplexed Bus
Signal Type: Input/Output (three-state capable)
Both address and data information are multiplexed onto these signals. Each bus transaction consists of an address
phase followed by one or more data phases. Data can be either read or written in bursts. The address is transferred
during the first clock cycle of a bus transaction. When the Little Endian format is selected, PAD[31:24] is the
MSB of the DWORD; when Big Endian is selected, PAD[7:0] contains the MSB. When the device is an initiator,
these signals are always outputs during the address phase. They remain outputs for the data phase(s) in a write
transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs
during the address phase. They remain inputs for the data phase(s) in a read transaction and become outputs for a
write transaction. When the device is not involved in a bus transaction, these signals remain three-stated. These
signals are always updated and sampled on the rising edge of PCLK.