Avago Technologies LSI53C1010 - Manual (Page 99)

Instruction Descriptions 3-59
Field(s) This command has the following fields:
The values in Table 3.14 define the SCSI information transfer phase. The
LSI53C10XX chips, with dual transition timing capabilities define two
transfer phases, ST for single transition timing, and DT for dual transition
timing.
Figure 3.17 RETURN Format
31 30 29 27 26 24 23 22 21 20 19 18 17 16 15 8 7 0
DCMD Register DBC Register
Instr
Type
Opcode SCSI Phase R
Carry
Test
R True
Comp
Data
Comp
Phase
Wait Mask Data
1 0 0 1 0 x x x 0 0 0 0 x x x x x x x x x x x x x x x x x x x x
31 0
DSPS Register
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Opcode Transfer Control, Return instruction.
SCSI Phase These bits reflect the actual values of the SCSI phase lines.
Table 3.14 SCSI Phase Bit Values (RETURN Format)
1
Phase Message Command/Data Input/Output
DATA_OUT
2
(ST_DATA_OUT)
3
0 0 0
DATA_IN
2
(ST_DATA_IN)
3
0 0 1