Avago Technologies LSI53C1010 - Manual (Page 218)

9-20 SCRIPTS Programming Topics
9.5.2 Registers
The registers that are used for detecting or defining interrupts are the
ISTAT, SIST0, SIST1, DSTAT, SIEN0, SIEN1, and DIEN.
9.5.2.1 ISTAT
Note: LSI53C896 and newer chips have two ISTAT registers.
Refer to your chip technical manual for specific information
regarding ISTAT. If your chip has two ISTAT registers, the
instructions below refer to ISTAT0.
ISTAT registers are the only registers that can be accessed as slaves
during SCRIPTS operation. Therefore, they are the registers polled when
polled interrupts are used. It is also the first register that should be read
when the IRQ/ pin has been asserted in response to a hardware
interrupt. The INTF (Interrupt on the Fly) bit should be the first interrupt
serviced. It must be written to one that is to be cleared. This interrupt
must be cleared before servicing any other interrupts. If the SIP bit in the
ISTAT register is set, then a SCSI type interrupt has occurred and the
SIST0 and SIST1 registers should be read. If the DIP bit in the ISTAT
register is set, then a DMA type interrupt has occurred and the DSTAT
register should be read. SCSI type and DMA type interrupts may occur
simultaneously, so in some cases both SIP and DIP may be set.
9.5.2.2 ISTAT1
Note: LSI53C896 and newer only.
This register contains two read-only bits, FLSH and SRUN. When set,
these bits indicate whether the chip is flushing data from the DMA FIFO
and if the SCRIPTS engine is currently fetching and executing SCRIPTS
instructions, respectively. Writes do not affect the value of these bits. The
other nonreserved bit in this register is SI, the synch interrupt disable bit.
Setting this bit disables the INTA/ pin for Function A and the INTB/ pin
for Function B. Clearing this bit enables normal operation of the INTA/ (or
INTB/) pin. If the INTA/ (or INTB/) is already asserted and this bit is set,
INT remains asserted until the interrupt is serviced. At this point the
interrupt line is blocked for future interrupts until this bit is cleared. In
addition, this bit may be read and written while SCRIPTS are executing.