Avago Technologies LSI53C1010 - Manual (Page 226)

9-28 SCRIPTS Programming Topics
9.6.2 Ultra Enable Bit
The Ultra Enable bit (also known as the Fast-20 Enable bit) adjusts the
chip’s timing to be compliant with the Fast-20 proposed standard. It
should be set when the synchronous transfer period is less than 100 ns
and cleared when it is greater than or equal to 100 ns.
9.6.3 Loading the New Register Values
Since the Ultra Enable bit and the clock dividers are in the SCNTL3 and
SXFER registers, these registers can be automatically loaded during a
selection or reselection by using Table Indirect Addressing. This allows
the chips to transparently talk with any combination of Ultra, Ultra2,
Ultra3, and Fast SCSI devices on the same SCSI bus.
9.6.4 Negotiating Synchronous Transfers
The easiest way to calculate the synchronous transfer period is by
multiplying the clock period by the clock divider values. For example, a
40 MHz clock is a 25 ns period. (25 ns) x (1) x (4) = 100 ns, which is
the Fast SCSI-2 synchronous transfer period.
If you use an 80 MHz clock (12.5 ns period) and are negotiating for Fast
SCSI-2, rather than Ultra SCSI, program the SCF bits for SCLK/2 and
the XFERP bits for 4, the resulting period is (12.5 ns) x (2) x (4) = 100 ns.
The SCSI-2 specification states that synchronous transfer rates must be
a multiple of 4 ns. However, with an 80 MHz clock, the period must be a
multiple of 12.5 ns. Ultra SCSI is defined to be a 20 megatransfers per
second maximum, which would be a 50 ns period. Since 50 ns is not a
multiple of 4, most SCSI devices cannot negotiate for this exact rate.
Unless future revisions of the standard make a different
recommendation, most devices will probably negotiate for a 48 ns period.
The SCRIPTS processor cannot be programmed for a 48 ns period since
it is not a multiple of 12.5 ns. Therefore driver programs should specify
a 50 ns period and the chip should negotiate for a 48 ns period. This is
acceptable because the SCSI-2 specification allows data to be
transferred at a slower rate than what is negotiated for, but not faster.
To program the chip for a full Ultra SCSI transfer rate of 50 ns using the
required 80 MHz clock, program the SCF bits for SCLK/1 and select an
XFERP of 4. This comes out to (12.5 ns) x (1) x (4) = 50 ns.