Avago Technologies LSI53C1010 - Manual (Page 69)

Instruction Descriptions 3-29
Field(s) This command has the following fields:
The values in Table 3.8 define the SCSI information transfer phase. The
LSI53C10XX chips, with dual transition timing capabilities define two
transfer phases, ST for single transition timing, and DT for dual transition
timing.
Register
Definition(s) The information listed below describes the DBC and DSPS registers:
Instruction
Type Transfer Control.
Opcode Jump instruction.
SCSI Phase These bits reflect the actual values of the SCSI phase lines.
Table 3.8 SCSI Phase Bit Values (JUMP Format)
1
1. 0 - False, negated; 1 - True, asserted. For these phases, SEL is negated and
BSY is asserted.
Phase Message Command/Data Input/Output
DATA_OUT
2
(ST_DATA_OUT)
3
2. All chips except LSI53C10XX.
3. LSI53C10XX chips.
0 0 0
DATA_IN
2
(ST_DATA_IN)
3
0 0 1
COMMAND 0 1 0
STATUS 0 1 1
RES4
4
(DT_DATA_OUT)
3
4. RES4 and RES5 are reserved SCSI phases except in the LSI53C10XX chips.
1 0 0
RES5
4
(DT_DATA_IN
)3
1 0 1
MESSAGE_OUT 1 1 0
MESSAGE_IN 1 1 1
Relative
Address The Relative Addressing Mode indicates that the 24-bit
address value in the instruction is to be used as an offset from
the current DSP address (which is pointing to the next
instruction, not the one currently executing).