Avago Technologies LSI53C1010 - Manual (Page 103)

Instruction Descriptions 3-63
Example SELECT host_1, sel_addr
SELECT FROM entry_2, sel_addr
Field(s) This command has the following fields:
Register
Definition(s) The information listed below describes the DBC and DSPS registers.
Description The chip waits for Bus Free, arbitrates for the SCSI bus, then performs
a selection. If the chip loses arbitration it repeats the process until it is
successful, unless there is a bus initiated interrupt. After winning
Figure 3.18 SELECT Format
31 30 29 27 26 25 24 23 20 19 16 15 0
DCMD Register DBC Register
Instr
Type
Opcode Relative
Table
Indirect
Select with
ATN
R SCSI ID R
0 1 0 0 0 0 0 x 0 0 0 0 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0
DSPS Register
Destination Address
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Instruction
Type I/O.
Opcode Select instruction.
Relative
Mode Indicates that the 24-bit address is an offset from the current
program counter.
Table Indirect
Mode Indicates that the SCSI ID and synchronous and wide
parameters should be loaded offset from the Data Structure
Address.
Select with
ATN Indicates whether or not the SCSI ATN/ signal should be
asserted.
SCSI ID Identifies the SCSI target to be selected. This 4-bit field
specifies the encoded destination ID. This field is reserved if
table indirect mode is used.
Destination
Address Specifies the memory address to fetch the next instruction if
the chip is selected or reselected during the selection.