Avago Technologies LSI53C1010 - Manual (Page 108)

3-68 The SCSI SCRIPTS Processor Instruction Set
4 bytes. The number of bytes to store is indicated by the low order bits
in the first Dword of the instruction, as illustrated in
Table 3.15 .
Notes The register address and memory address must have the same byte
alignment and the byte count set so that it does not cross Dword
boundaries. The memory address may not map back to the chip
operating registers, although it may map back to a location in the
SCRIPTS RAM. If these conditions are violated, a PCI illegal read/write
cycle will occur and the chip will issue an Interrupt (Illegal Instruction
Detected) immediately following, because the intended operation did not
happen.
Legal Forms STORE register, byte_count, destination_address
STORE register, byte_count, DSAREL (destination_address)
STORE NOFLUSH register, byte_count, destination_address
3.2.20 WAIT DISCONNECT
WAIT DISCONNECT
Supported by All LSI Logic SCSI SCRIPTS Processors.
Definition Wait for SCSI bus disconnect.
Operands This command has the following operands:
None.
Example WAIT DISCONNECT
Table 3.15 Low Order Bit Options
DBC Bits [17:16]
(Register Address bits A1-A0) Number of Bytes to Store
00 1, 2, 3, or 4
01 1, 2, or 3
10 1 or 2
11 1