Avago Technologies LSI53C1010 - Manual (Page 225)

Migrating Existing Software to Ultra, Ultra2, and Ultra3 SCSI 9-27
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SCNTL3 register SCF bits – adjust the bit values to reflect the SCLK
frequency, doubled or quadrupled if applicable.
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SXFER register XFERP bits – adjust the bit values to reflect the
desired divider values for the synchronous period.
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Adjust the Clock input as required for the SCSI processor being
used.
•
With the LSI53C860, add an external 80 MHz SCSI clock.
•
With the LSI53C875, use an 80 MHz external SCSI clock or use an
external 40 MHz clock and enable the SCSI clock doubler.
•
With the LSI53C895, use an 80 MHz clock for Ultra SCSI or use an
external 40 MHz clock with the clock quadrupler for Ultra2 SCSI.
•
The LSI53C885 and LSI53C876 require a 40 MHz clock and use of
the clock doubler.
•
Ultra Enable bit, SCNTL3 register – set this bit to enable Ultra SCSI
or Ultra2 SCSI transfers.
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SCNTL4 U3EN bit set to enable Ultra3 (LSI53C10XX only).
9.6.1 Clock Divider Bits
Two registers divide down the clock. The first is the SCNTL3 register.
Except for the Ultra3 chips, the CCF bits determine the SCSI core speed
used for asynchronous transfers and any other timings (such as selection
time-out). These bits are set based on the input clock frequency and do
not change. The SCF bits determine the timing for synchronous transfers
and can be changed whenever the SCRIPTS processor connects to a
different device on the SCSI bus.
The SCF bits in the SCNTL3 register, in conjunction with the XFERP bits
in the SXFER register, determine the synchronous period. To get a
transfer rate of 10 Mbytes/s with a 40 MHz clock, program the SCF bits
to 0b001 for a divide by one factor and then program the XFERP bits for
0b000 for a divide by 4 factor. Forty MHz divided by 1 and then divided
by 4 is 10 Mbytes/s. Other combinations of these two sets of bits select
a variety of synchronous transfer rates. For more information on the
supported bit combinations, see the clock divider bit descriptions in your
chip technical manuals.
The LSI53C10XX has only a 40 MHz clock with no dividers.