Avago Technologies LSI53C1010 - Manual (Page 274)

13-4 New SCRIPTS Processor Features
13.6.2 Registers
This is a list of the registers that are involved with Phase Mismatch
Handling.
•
Phase Mismatch Jump Address one, PMJAD1 (0xC0–0xC3) R/W
This register contains the address the SCRIPTS engine jumps to on
phase mismatch if WSR is clear or during a data out phase.
•
Phase Mismatch Jump Address two, PMJAD2 (0xC4–0xC7) R/W
This register contains the address to which the SCRIPTS engine
jumps on phase mismatch if WSR is set or during a data in phase.
•
Remaining Byte Count, RBC (0xC8–0xCB) R/W
This register contains the remaining byte count for the block move
that was executing when the phase mismatch occurred. The upper
byte also contains an opcode for a direct or indirect block move or
the upper byte of the table entry for table indirect block moves.
•
Updated Address, UA (0xCC–0xCF) R/W
This register contains the updated source/destination data address
for the block move that was executing when the phase mismatch
occurred. If there is a byte in SWIDE, then this register points to the
address where the byte should be stored. The address must be
incremented manually.
•
Entry Storage Address, ESA (0xD0–0xD3) R/W
For direct/indirect block moves, this register contains the address of
the block move instruction that was executing when the phase
mismatch occurred. For table indirect block moves this register
contains the address of the table entry being used when the phase
mismatch occurred.
•
Instruction Address, IA (0xD4–0xD7) R/W
This register always contains the address of the block move that was
executing when the phase mismatch occurred.
•
SCSI Byte Count/SBC (0xD8–0xDA) Read only
This register counts bytes transferred to/from the SCSI bus during
any given block move. Resets to zero at the start of each block move.
Will be off by one in the case of an odd byte count wide transfer or