Avago Technologies LSI53C1010 - Manual (Page 203)

Loopback Mode 9-5
•
STEST2
– Bits [4:3] should be set to turn on the Loopback Mode and set
the SCSI pins to high impedance, so that signals are not
asserted on to the SCSI bus. Bit 4 is reserved in the
LSI53C10XX.
– Bits [7:6] and 0 do not affect the loopback operation, but should
remain cleared.
– Bits 5 and [2:1] will not affect the running of the Loopback Mode.
Bit 2 is reserved in the LSI53C10XX.
•
DCNTL
– Bit 4 should be set to turn on the Single Step Mode.
This allows the target program to monitor when an initiator
SCRIPTS instruction has completed.
– Bits [3:2] should be cleared, and the remaining bit values will not
affect the running of the Loopback Mode.
•
DIEN
– Bit 3 should be set to enable single step interrupts.
This bit works in conjunction with the Single Step Mode bit to
allow for monitoring of SCRIPTS instruction completion.
– The remaining bit values in this register do not affect the running
of the Loopback Mode.
9.2.1 Loopback Example – Selection
The example in Figure 9.3 demonstrates selection in SCSI Loopback
Mode. It provides all the general code required to implement any of the
various SCSI sequences in the Loopback Mode. This example assumes
that the chip was initialized as described above. The initiator instructions
are implemented using the SCRIPTS processor and SCRIPTS. The
target instructions are implemented using the CPU and a “C” program.
When a SCRIPTS routine is executing, a waiting period is required to
fetch the SCRIPTS instructions. This fetch time must be taken into
account when writing the loopback code. To ensure proper operation, a
delay should be inserted directly after SCRIPTS instructions have started
executing. After the DSP register (0x2C–0x2F) is initialized with a
SCRIPTS instruction address, the chip registers cannot be accessed