Avago Technologies LSI53C1010 - Manual (Page 275)

Phase Mismatch Handling 13-5
when during a wide send and there is a chained byte from a previous
transfer.
•
Cumulative SCSI Byte Count, CSBC (0xDC–0xDF) R/W
This loadable register counts bytes transferred across the SCSI bus
independent of the block move executing. Only counts bytes during
data phase transfers.
The SWIDE byte must be flushed manually. Phase Mismatch that occurs
when WSS is set condition is handled. PMJAD1 and PMJAD2 are fully
static. RBC, UA, ESA and IA only change when a phase mismatch
occurs. SBC and CSBC change from block move to block move. You can
get stuck in a tight loop in SCRIPTS if you are not careful.
13.6.3 SCRIPTS Example
The following example is a Direct/Table indirect BMOV example, with
PMJCTL = 0
HandlePhaseMismatchNoWSR:
CALL REL(Save_cumulative_byte_count)
CALL REL(Get_msg_bytes_and_ensure_save_pointers)
; Update the Direct/Table Indirect Scatter Gather entry
Update_SG_entry:
; Modify Mem to Mem move to update Table indirect entry
STORE ESA0, 4, Mem2Mem_to_be_patched + 8
; Move the new byte count and address to the entry
Mem2Mem_to_be_patched:
MOVE MEMORY 8, RBC_addr, 0
JUMP REL(Do_code_architecture_specific_update)
HandlePhaseMismatchWSR:
CALL REL(Save_cumulative_byte_count)
; If here there is a byte in SWIDE to be moved
; Patch the BMOV that will flush SWIDE
STORE UA0, 4, SWIDE_patch+4
SWIDE_patch:
; Using a BMOV here is optimal due to the fact
; that there are no alignment restrictions as