Avago Technologies LSI53C1010 - Manual (Page 15)

Contents xv
Chapter 13 New SCRIPTS Processor Features
13.1 Improved FIFO Flushing 13-1
13.2 Larger FIFO 13-2
13.3 New ISTAT Registers 13-2
13.4 New Scratch Registers 13-2
13.5 New Load/Store Feature 13-2
13.6 Phase Mismatch Handling 13-3
13.6.1 Control Bits 13-3
13.6.2 Registers 13-4
13.6.3 SCRIPTS Example 13-5
13.7 64-Bit SCRIPTS Addressing 13-6
13.7.1 Control Bits 13-6
13.7.2 Block Move 13-7
13.7.3 Direct Block Move 13-7
13.7.4 Mode 0 Table Indirect Block Move 13-7
13.7.5 Mode 1 Table Indirect Block Move 13-8
13.7.6 Table Indirect Block Move Summary 13-10
13.7.7 LSI53C1010/LSI53C1010R 13-10
Appendix A NASM Error Messages
Appendix B Multithreaded SCRIPTS Example
Appendix C Glossary of Terms and Abbreviations
Index
Customer Feedback
Figures
1.1 Single Channel Block Diagram 1-6
1.2 Dual Channel Block Diagram 1-6
1.3 Typical SCRIPTS Operation 1-9
2.1 Overview of Assembling SCSI SCRIPTS 2-5