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Figure9.5 byte transfer, Byte transfer – Avago Technologies LSI53C1010 User Manual

Page 206

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9-8

SCRIPTS Programming Topics

code, it can also be used as a separate function. It can also be used for
any generic data transfer between the initiator and the target, whenever
the processor is executing a Block Move instruction.

Figure 9.5

Byte Transfer

Assertion of the SREQ/ signal is the first step performed by this code.
SREQ/ is asserted by keeping the phase bits the same and setting the
SREQ/ bit in the SOCL register. This works for an initiator to target data
transfer (DATA OUT, MESSAGE OUT, or COMMAND phase). To transfer
from the target to the initiator (DATA IN, MESSAGE IN, or STATUS
phase) place the data into the SODL register before asserting SREQ/.
Because the processor clocks asynchronous data in on the rising edge
of SACK/, data corruption results if this procedure is not followed. If
SREQ/ is asserted, the processor immediately asserts ACK/ and clocks
in the data in the SOCL register. If the data has not been placed into the
SOCL register then incorrect data will be clocked in.

After asserting SREQ/, the initiator polls the SBCL register for SACK/
assertion. Subsequently, the target reads the SBDL register. It also
deasserts SREQ/ using the SOCL register and polls the SBCL register
for SACK/ deassertion of SACK/ by the initiator. The byte received by the
target is verified with the byte sent by the initiator.

The code section in

Figure 9.6

shows the final step of the selection

procedure in the Loopback Mode. This selection procedure could be
placed into a function, as could procedures that implement command,
status, message in, and data transfer phases. Upon doing this, full SCSI
sequences could be implemented in the Loopback Mode by various
function calls in the proper order.

/*TARGET, Get Message Byte */
/*TARGET, assert REQ, maintain all other SCSI signals*/
siop_reg[SOCL] |=0x80;
/*TARGET, wait for ACK*/
while ((siop_reg[SBCL] & 0x40) !=0)
msg_out_buf = siop_reg[SBDL]; /*read the data bus*/
siop_reg[SOCL] &=0x7f; /*deassert REQ*/
while ((siop_reg[SBCL] & 0x40) !=0) /* wait for ACK*/
/* verify message byte */
if (msg_out_buf !=identify_buf) {
loop_err = 1;

}

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