Avago Technologies LSI53C1010 - Manual (Page 204)

9-6 SCRIPTS Programming Topics
until the instruction has been fetched and begins executing. This delay
time must include:
•
Host arbitration
•
SCRIPTS instruction fetch
•
SCRIPTS instruction execution or internal bus moves
These delay times are system dependent due to host arbitration times,
host bus width, and chip clock speed.
Figure 9.3 Loopback Mode
In this section of code, the Initiator Select SCRIPTS routine is started by
writing the address of the Select instruction to the DSP. A delay is
inserted to ensure that the SIOP has time to fetch the instruction. Polling
the SBCL register determines when SEL/ is active and selecting itself.
As shown in Figure 9.4 , the variable siop_reg should be defined as a
volatile pointer to the chip registers. This ensures that the registers are
not shadowed internally by the CPU. Polling the SBDL register
determines which SCSI ID bits are being driven. This is not a vital step
in the loopback selection process, since the SCRIPTS processor is
selecting itself. However, SBDL should be checked to make sure the
correct bits are driven on the SCSI data bus during normal selection. The
BSY/ bit is set in the SOCL register. This is a target operation performed
by the CPU. Polling the SEL/ bit of the SBCL register determines when
SEL/ is inactive. This indicates the initiator is properly responding to
BSY/ being asserted by the target.
/*Load DSP with address of Select w/ATN instruction*/
/* SELECT ATN tar_id, REL(This_wont_occur) */
write_longreg (DSP,SCRIPTS_sel_inst);
/* Delay to allow instruction to be fetched by SIOP */
delay(1); /* 1 ms delay, varies with system*/
/* TARGET, wait for SEL to go high and BSY to go low */
while ((siop_reg[SBCL] & 0x30) != 0x10;
/*TARGET, check ID, but really don’t care what it is */
printf(“Initiator: Selecting target ID
%x\n”,siop_reg[SBDL]);
/*TARGET, assert BSY*/
siop_reg[SOCL] = 0x20;
/*TARGET, wait for SEL to drop */
while ((siop_reg[SBCL] & 0x10) !=0);