Avago Technologies LSI53C1010 - Manual (Page 221)

Interrupt Handling 9-23
These interrupts are not needed for events that occur during high level
SCRIPTS operation.
9.5.4 Masking
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the SIEN0 and SIEN1 (for SCSI
interrupts) interrupt enable registers or the DIEN (for DMA interrupts)
interrupt enable register. How the chip responds to masked interrupts
depends on: whether polling or hardware interrupts are being used;
whether the interrupt is fatal or nonfatal; and whether the chip is
operating in Initiator or Target Mode.
If a nonfatal interrupt is masked and that condition occurs, SCRIPTS:
•
Continues execution
•
Sets the appropriate bit in the SIST0 or SIST1 register
•
Does not set the SIP bit in the ISTAT
•
Does not assert the IRQ/ pin
See Section 9.5.3, “Fatal vs. Nonfatal Interrupts,” for a list of the nonfatal
interrupts.
If a fatal interrupt is masked and that condition occurs, then SCRIPTS
stops execution, sets the appropriate bit in the DSTAT, SIST0, or SIST1
registers, and sets the SIP or DIP bits in the ISTAT. The IRQ/ pin is not
asserted.
When the chip is initialized, you must enable all fatal interrupts if you are
using hardware interrupts. If a fatal interrupt is disabled and that interrupt
condition occurs, SCRIPTS halts. The system will not detect this unless
it times out and checks the ISTAT after a certain period of inactivity.
If the ISTAT register is being polled, instead of using hardware interrupts,
then masking a fatal interrupt has no impact. The SIP and DIP bits in the
ISTAT inform the system of interrupts, not the IRQ/ pin.
Masking an interrupt after IRQ/ is asserted will not deassert IRQ/.