Avago Technologies LSI53C1010 - Manual (Page 224)

9-26 SCRIPTS Programming Topics
5. If both the SIP and DIP bits are set, read the SIST0, SIST1, and
DSTAT registers to clear the SCSI and DMA interrupt condition and
get the interrupt status.
If using 8-bit reads of the SIST0, SIST1, and DSTAT registers to clear
interrupts, insert a 12 CLK delay between the consecutive reads to
ensure that the interrupts clear properly. Both the SCSI and DMA
interrupt conditions should be handled before leaving the ISR. It is
recommended that the DMA interrupt be serviced before the SCSI
interrupt, because a serious DMA interrupt condition could influence
how the SCSI interrupt is acted upon.
When using polled interrupts, go back to Step 1 before leaving the
interrupt service routine, in case any stacked interrupts moved in when
the first interrupt was cleared. When using hardware interrupts, the IRQ/
pin will be asserted again if there are any stacked interrupts. This should
cause the system to re-enter the interrupt service routine.
9.6 Migrating Existing Software to Ultra, Ultra2, and Ultra3
SCSI
Current SCSI technology extends the Fast SCSI-2 specification to allow
synchronous transfer periods to be negotiated down as low as 50 ns
(Ultra), 25 ns (Ultra2/3). Ultra3 SCSI supports dual transition clocking for
an effective period of 12.5 ns. This allows a maximum transfer rate of
20 Mbytes/s on an 8-bit SCSI bus or 40 Mbytes/s on a wide SCSI bus
for Ultra SCSI, and 40 Mbytes/s on an 8-bit bus, 80 Mbytes/s on a wide
SCSI bus for Ultra2 SCSI and 160 Mbytes/s for Ultra3. Refer to
Chapter 1, “Using the Programming Guide,” to determine which chips
support Ultra/2/3 SCSI.
To achieve transfer rates reflecting current SCSI specifications, existing
software programs must be updated to reflect changes in the following
areas of the SCRIPTS processor. Additional minor changes may be
needed to migrate existing software to support all the features in the new
device:
•
SCNTL3 register CCF bits – adjust the bit values to reflect the
desired clock divider (not the LSI53C1010 or LSI53C1010R).