Avago Technologies LSI53C1010 - Manual (Page 209)

Byte Recovery on Target Disconnect 9-11
make this calculation, subtract the seven least significant bits of the DBC
register from the 7-bit value of the DFIFO register. AND the result with
0x7F for a byte count between zero and the FIFO size.
If the DMA FIFO size is set to the extended size, subtract the 10 least
significant bits of the DBC register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register
and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a
byte count between zero and the extended FIFO size.
Read bit 5 in the SSTAT0 and SSTAT2 registers to determine if any bytes
are left in the SODL register. If bit 5 is set in the SSTAT0 or SSTAT2
register then the least significant byte or the most significant byte in the
SODL register is full, respectively. Checking this bit also reveals bytes left
in the SODL register from a Chained Move operation with an odd byte
count.
9.3.1.2 Synchronous SCSI Send
If the DMA FIFO size is set to the default size, look at the DFIFO and
DBC registers and calculate if there are bytes left in the DMA FIFO. To
make this calculation, subtract the seven least significant bits of the DBC
register from the 7-bit value of the DFIFO register. AND the result with
0x7F for a byte count between zero and the FIFO size.
If the DMA FIFO size is set to the extended size, subtract the 10 least
significant bits of the DBC register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register
and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a
byte count between zero and the FIFO size.
Read bit 5 in the SSTAT0 and SSTAT2 registers to determine if any bytes
are left in the SODL register. If bit 5 is set in the SSTAT0 or SSTAT2
register then the least significant byte or the most significant byte in the
SODL register is full, respectively. Checking this bit also reveals bytes left
in the SODL register from a Chained Move operation with an odd byte
count.
Read bit 6 in the SSTAT0 and SSTAT2 registers to determine if any bytes
are left in the SODR register. If bit 6 is set in the SSTAT0 or SSTAT2
register then the least significant byte or the most significant byte in the
SODR register is full, respectively.