Avago Technologies LSI53C1010 - Manual (Page 219)

Interrupt Handling 9-21
9.5.2.3 SIST0 and SIST1
The SIST0 and SIST1 registers contain the SCSI type interrupt bits.
Reading these registers determines which condition or conditions caused
the SCSI type interrupt and clears that SCSI interrupt condition. If the
chip is receiving data from the SCSI bus and a fatal interrupt condition
occurs, the SCRIPTS processor attempts to send the contents of the
DMA FIFO to memory before generating the interrupt. If the processor is
sending data to the SCSI bus and a fatal SCSI interrupt condition occurs,
data could be left in the DMA FIFO. Under these circumstances, check
the DMA FIFO Empty (DFE) bit in DSTAT. If this bit is cleared, set the
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before
continuing. The CLF bit is bit 2 in CTEST3. The FLF bit is bit 3 in
CTEST3. The CSF bit is bit 1 in STEST3.
9.5.2.4 DSTAT
The DSTAT register contains the DMA type interrupt bits. Reading this
register determines which condition or conditions caused the DMA type
interrupt, and clears that DMA interrupt condition. Bit 7 in DSTAT, DFE
(DMA FIFO Empty), is purely a status bit. This bit does not generate an
interrupt under any circumstances and is not cleared when read. DMA
interrupts do not flush either the DMA or SCSI FIFOs before generating
the interrupt, so the DFE bit in the DSTAT register should be checked
after any DMA interrupt. If the DFE bit is cleared, then the FIFOs must
be cleared by setting the CLF (Clear DMA FIFO) and CSF (Clear SCSI
FIFO) bits, or flushed by setting the FLF (Flush DMA FIFO) bit.
9.5.2.5 SIEN0 and SIEN1
The SIEN0 and SIEN1 registers are the interrupt enable registers for the
SCSI interrupts in the SIST0 and SIST1 registers.
9.5.2.6 DIEN
The DIEN register is the interrupt enable register for DMA interrupts in
DSTAT.