Avago Technologies LSI53C1010 - Manual (Page 207)

Byte Recovery on Target Disconnect 9-9
Figure 9.6 Loopback Mode Selection Procedure
Selection without ATN/, requires only assertion of the next phase and
waiting for a single step interrupt. The MSG/, C_D/, and I_O/ signals are
set to the command phase using the SOCL register. BSY/ is also kept
asserted. The SIP and DIP bits in the ISTAT register are polled for a
single step interrupt and any other interrupts that may have occurred.
These interrupts are cleared by reading the SIST1, SIST0, and DSTAT
registers. The single step interrupt is cleared by reading the DSTAT
register, but depending on the settings in the SIEN and DIEN registers,
other interrupts may occur. You can safely clear all interrupts, as any
pending interrupts would inhibit the execution of remaining SCRIPTS
instructions. The example uses a polled interrupt procedure. If hardware
interrupts are used then this would be handled in an interrupt service
routine. After code execution, the chip is in a state to transfer command
bytes using the generic byte transfer code given earlier.
9.3 Byte Recovery on Target Disconnect
There are three potential instances of disconnect. The first is during a
Data Read, when a SCSI device may disconnect while it is seeking the
data that was requested. This is very common, occurring when a SCSI
disk drive performs a seek operation. Seeks often take many
milliseconds and it is inefficient for the disk drive to stay active on the
bus while transferring nothing. The second case may occur after a SCSI
device completes a write operation and disconnects to empty its buffers
before returning its status and command complete messages.
else{ /*select without ATN*/
printf(“Initiator: Selecting without ATN.../n);
}
/*assert BSY and Command phase*/
siop_reg[SOCL} = 0x22;
/*wait for single step int.*/
while ((siop_reg[ISTAT] & 0x03) == 0);
/* clear all interrupts */
junk = siop_reg[SIST0];
junk = siop_reg[SIST1];
junk = siop_reg[DSTAT];
/*SELECTION COMPLETE*/