Avago Technologies LSI53C1010 - Manual (Page 273)

Phase Mismatch Handling 13-3
13.6 Phase Mismatch Handling
Phase Mismatch Handling eliminates the Phase Mismatch Interrupt. The
default setting for this feature is OFF. Bit 7 of CCNTL0 (offset 0x56)
enables the feature. Phase Mismatch Handling has the following
features.
•
Performs all necessary byte count/pointer calculations then jumps to
a SCRIPTS phase mismatch handler.
•
Supports two jump vectors with programmable jump control.
•
Supports jump enable/disable during nondata phases.
•
Supports Loadable Cumulative SCSI Byte Count to maintain total
bytes transferred for a given I/O.
Note: Overhead to jump is approximately 16 PCI clocks, not
including time to flush.
13.6.1 Control Bits
This section describes the control bits used for phase mismatch
handling. All bits are located in CCNTL0 (0x56).
•
Bit 7: ENPMJ, Enable Phase Mismatch Jump (default = 0)
•
Bit 6: PMJCTL, Phase Mismatch Jump Control (default = 0)
This bit controls which decision mechanism is used when jumping on
phase mismatches. When PMJCTL is clear, PMJAD1 is used when
WSR is clear, PMJAD2 when WSR is set. When PMJCTL is set,
PMJAD1 is used during data out phases, PMJAD2 used during data
in phases.
•
Bit 5: ENNDJ, Enable Nondata Jump (default = 0)
When this bit is clear a Phase Mismatch interrupt is generated on
nondata phase mismatches, such as Status, Msg In/Out, and
Command. When set, jumps are taken during nondata phases.
•
Bit 4: DISFC, Disable Auto FIFO Clear (default = 0)
This bit disables automatic FIFO clearing on data out phase
mismatches and disables enhanced flushing.