Avago Technologies LSI53C1010 - Manual (Page 222)

9-24 SCRIPTS Programming Topics
9.5.5 Stacked Interrupts
The SCRIPTS processor stacks interrupts if they occur in rapid
succession. If the SIP or DIP bits in the ISTAT register are set (first level),
then at least one pending interrupt exists. Any future interrupts are
stacked in extra registers behind the SIST0, SIST1, and DSTAT registers
(second level). When two interrupts have occurred and the two levels of
the stack are full, any further interrupts set additional bits in the extra
registers behind the SIST0, SIST1, and DSTAT registers. When the first
level of interrupts is cleared, the subsequent interrupts move into the
SIST0, SIST1, and DSTAT registers. After clearing the first interrupt by
reading the appropriate register, the IRQ/ pin deasserts for a minimum
of three CLKs, the stacked interrupt(s) move into the SIST0, SIST1, or
DSTAT registers, and the IRQ/ pin reasserts.
A masked nonfatal interrupt does not set the SIP or DIP bits. Therefore,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in the SIST0 register, but does not assert the IRQ/ pin.
Since no interrupt is generated, subsequent interrupts move right into the
SIST0 or SIST1 register instead of being stacked behind another
interrupt. On generation of another interrupt, the bit corresponding to the
earlier masked nonfatal interrupt remains set.
Two simultaneous interrupts cause a similar situation. Since stacking
does not occur until the SIP or DIP bits are set, a small timing window
exists in which multiple interrupts can occur. Under these circumstances,
the interrupts are not stacked. These could be multiple SCSI interrupts
(SIP set), multiple DMA interrupts (DIP set), or multiple SCSI and
multiple DMA interrupts (both SIP and DIP set).
As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. You must set either the Clear DMA
FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA interrupt occurs
and the DMA FIFO Empty (DFE) bit is not set. Any subsequent SCSI
interrupts are not posted until the DMA FIFO is cleared of data. These
‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is
empty.
9.5.6 Halting in an Orderly Fashion
When an interrupt occurs, the SCRIPTS processor attempts to halt in an
orderly fashion.