Avago Technologies LSI53C1010 - Manual (Page 276)

13-6 New SCRIPTS Processor Features
; there are in mem2mem moves or stores
CHMOV 1, 0, WHEN DATA_IN
; Now increment the data address
MOVE UA + 1 to UA
MOVE UA + 0 to UA WITH CARRY
MOVE UA + 0 to UA WITH CARRY
MOVE UA + 0 to UA WITH CARRY
; Jump back up to update the Scatter Gather entry
JUMP REL(Update_SG_entry)
13.7 64-Bit SCRIPTS Addressing
Three extended addressing modes are available.
•
Full 64-bit data addressing for direct block moves (bit enabled).
•
64-bit indexed data addressing mode for table indirect block moves
(bit enabled).
•
40-bit data addressing mode for table indirect block moves (bit
enabled).
Six selectors provide the upper 32-bits of a 64-bit address. If a selector
is zero, a single address cycle is issued. If the selector is nonzero then
a dual address cycle is issued. Five of the selectors are fully static and
the remaining one is semidynamic. For table index mode, the 16 Scratch
registers are also available.
Note: Crossing 4-Gbyte boundaries is not supported.
13.7.1 Control Bits
Control bits for 64-bit addressing are located in CCNTL1 register (0x57).
•
Bit 2: 64TIMOD, 64-bit Table Indirect Index mode (default = 0)
Clear: D[28:24] of first Dword of table entry is used as an index to
select one of 22 selectors (ScratchC–R, MMRS, MMWS, SFS, DRS,
DBMS, or SBMS).
Set: D[31:24] of first Dword of table entry is used as AD[39:32] to
form a 40-bit address.