Avago Technologies LSI53C1010 - Manual (Page 223)

Interrupt Handling 9-25
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If it is in the middle of an instruction fetch, the fetch will be
completed, except in the case of a Bus Fault. Execution will not
begin, but the DSP points to the next instruction since it is updated
when the current instruction is fetched.
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If the DMA direction is a write to memory and a SCSI interrupt
occurs, the SCRIPTS processor attempts to flush the DMA FIFO to
memory before halting. Under any other circumstances only the
current cycle will be completed before halting, so the DFE bit in the
DSTAT register should be checked to see if any data remains in the
DMA FIFO.
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SCSI SREQ/SACK handshakes that have begun will be completed
before halting.
•
The SCRIPTS processor attempts to clean up any outstanding
synchronous offsets before halting.
•
In the case of Transfer Control Instructions, once execution begins it
will not halt until completion.
•
If the instruction is a JUMP/CALL WHEN/IF , the DSP is
updated to the transfer address before halting.
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All other instructions may halt before completion.
9.5.7 Sample Interrupt Service Routine
The following is a sample of an interrupt service routine. It can be
repeated if polling is used, or should be called when the IRQ/ pin is
asserted if hardware interrupts are used.
1. Read ISTAT (or ISTAT0 as appropriate if your system has a newer
chip).
2. If the INTF bit is set, write it to a one to clear this status.
3. If only the SIP bit is set, read the SIST0 and SIST1 registers to clear
the SCSI interrupt condition and get the SCSI interrupt status.
The bits in the SIST0 and SIST1 registers define the interrupt(s) and
determine what action is required to service them.
4. If only the DIP bit is set, read the DSTAT register to clear the interrupt
condition and get the DMA interrupt status.
The bits in the DSTAT register define the interrupt(s) and determine
what action is required to service them.