Altera Avalon Verification IP Suite - Manual (Page 98)

get_clken()
logic get_clken() Prototype:
Verilog HDL: None
VHDL: clken , bfm_id , req_if(bfm_id)
Arguments:
logic
Returns:
Returns the clock enable signal status. Description:
Verilog HDL, VHDL Language support:
get_version()
string get_version() Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
String
Returns:
Returns BFM version as a string of three integers separated by periods. For
example, version 10.1 sp1 is encoded as "10.1.1". Description:
Verilog HDL Language support:
get_command_address()
bit [AV_ADDRESS_W-1:0] get_command_address()
Prototype:
Verilog HDL: None
VHDL: command_address , bfm_id , req_if(bfm_id)
Arguments:
bit [AV_ADDRESS_W-1:0]
Returns:
Queries the received command descriptor for the transaction address. Description:
Verilog HDL, VHDL Language support:
get_command_arbiterlock()
bit get_command_arbiterlock()
Prototype:
Verilog HDL: None
VHDL: command_arbiterlock , bfm_id , req_if(bfm_id)
Arguments:
bit
Returns:
Queries the received command descriptor for the transaction arbiterlock. Description:
Verilog HDL, VHDL Language support:
Avalon-MM Monitor Altera Corporation
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get_clken() 7-26