Altera Avalon Verification IP Suite - Manual (Page 60)

get_command_arbiterlock()
bit get_command_arbiterlock()
Prototype:
Verilog HDL: None
VHDL: command_arbiterlock , bfm_id , req_if(bfm_id)
Arguments:
bit
Returns:
Queries the received command descriptor for the transaction arbiterlock. Description:
Verilog HDL, VHDL Language support:
get_command_burst_count()
[AV_BURSTCOUNT_W-1:0] get_command_burst_count()
Prototype:
Verilog HDL: None
VHDL:
command_burst_count
,
bfm_id
,
req_if(bfm_id)
Arguments:
[AV_BURSTCOUNT_W-1:0] Returns:
Queries the received command descriptor for the transaction burst count. Description:
Verilog HDL, VHDL Language support:
get_command_burst_cycle()
int get_command_burst_cycle()
Prototype:
Verilog HDL: None
VHDL:
command_burst_cycle
,
bfm_id
,
req_if(bfm_id)
Arguments:
Int Returns:
The slave BFM receives and processes write burst commands as a sequence of
discrete commands. The number of commands corresponds to the burst count.
A separate command descriptor is constructed for each write burst cycle. Each
command corresponds to a partially completed burst. This method returns a burst
cycle field telling the testbench which burst cycle was active when this descriptor
was constructed. This facility enables the testbench to query partially completed
write burst operations.The testbench can query the write data word on each burst
cycle as it arrives. Consequently, the testbench can begin to process it immediately
rather than waiting until the entire burst has been received. This facility means
you can implement pipelined write burst processing in the testbench. Description:
Verilog HDL, VHDL Language support:
Avalon-MM Slave BFM Altera Corporation
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get_command_arbiterlock() 6-12