Altera Avalon Verification IP Suite - Manual (Page 84)

set_enable_a_register_incoming_signals()
set_enable_a_register_incoming_signals()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables an assertion that ensures
waitrequest
is asserted at all times and
deasserts a single clock cycle after a read or write transaction.
Description:
Verilog HDL Language support:
set_enable_a_waitrequest_during_reset()
set_enable_a_waitrequest_during_resetl()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void Returns:
Enables an assertion that ensures that
waitrequest
is asserted if
reset
is
asserted. Disabled when waitrequest is not supported.
Description:
Verilog HDL Language support:
set_enable_a_waitrequest_timeout()
set_enable_a_waitrequest_timeout()
Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables an assertion that ensures waitrequest is not asserted continuously
for more than maximum allowed timeout period. Disabled when either
waitrequest
is not supported or the maximum timeout period is less than
1.
Description:
Verilog HDL Language support:
Avalon-MM Monitor Altera Corporation
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set_enable_a_register_incoming_signals() 7-12