Altera Avalon Verification IP Suite - Manual (Page 203)

signal_result_driven
signal_result_driven
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that a result has been driven from the slave interface. Description:
Verilog HDL Language support:
signal_unknown_instruction_received
signal_unknown_instruction_received
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that a change has occured on the instruction interface and there is an
unknown value. Description:
Verilog HDL Language support:
Altera Corporation Nios II Custom Instruction Slave BFM
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15-13 signal_result_driven