Altera Avalon Verification IP Suite - Manual (Page 146)

set_enable_c_multiple_packet_per_cycle()
set_enable_c_multiple_packet_per_cycle() Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables a coverage point that ensures test coverage for number of transactions
that carry multiple packets per single cycle. It is disabled when packet
transmission is not supported. Description:
Verilog HDL Language support:
set_enable_c_non_valid_ready()
set_enable_c_non_valid_ready()
Prototype:
Verilog HDL:
Boolean
VHDL: N.A.
Arguments:
void Returns:
Enables a coverage point that ensures test coverage for the assertion of
valid
signal with different values for readyLatency.
RL**For more information, refer to the Avalon Interface Specifications .
Description:
Verilog HDL Language support:
set_enable_c_non_valid_non_ready()
set_enable_c_non_valid_non_ready()
Prototype:
Verilog HDL: Boolean
VHDL: N.A.
Arguments:
void
Returns:
Enables a coverage point that ensures test coverage for the deassertion of
both
ready
and
valid
. It is disabled when the
ready
signal is not supported.
Description:
Verilog HDL Language support:
Avalon-ST Monitor Altera Corporation
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