Altera Avalon Verification IP Suite - Manual (Page 221)

master BFM, include the package for this BFM in your test program. Packages are named:
component name>_vhdl_pkg
The VHDL BFM design and simulation flow is similar to the Verilog HDL flow, and involves the following
steps:
1. Create the system design in Qsys.
2. Generate the testbench design in the Qsys Generation tab. Qsys automatically assigns a unique ID (0 to
1023) to each VHDL BFM instance in the testbench design.
You can implement up to 1,024 instances of a particular BFM component. Note:
1. Open the testbench system in Qsys.
2. (Optional) Make changes as needed to the BFM, such as changing the BFM instance name or the
VHDL BFM ID. You change the ID with the VHDL BFM ID option.
The VHDL BFM ID is only applicable for VHDL BFMs. The parameter appears in the top-level HDL
for both Verilog HDL and VHDL files. However, Verilog HDL systems ignore this setting. Note:
1. Generate a VHDL simulation model of the testbench design.
2. Create a custom test program.
3. Compile and load the Qsys design and testbench in a simulator.
4. Run the simulation.
For information about creating a Verilog HDL testbench click on the link below.
Related Information
Avalon-ST Verilog HDL Testbench on page 16-1
Altera Corporation Avalon-MM Verilog HDL and VHDL Testbenches
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17-11 Using the VHDL BFMs