Altera Avalon Verification IP Suite - Manual (Page 215)

Figure 17-3: Avalon-MM Master0 and Slave0 Writes
tb.clk
tb.reset
m0_waitrequest
m0_write
m0_read
m0_readdatavalid
m0_address[12:0]
m0_burstcount[3:0]
m0_writedata[31:0]
m0_byteenable[3:0]
m0_readdata[31:0]
s0_address[9:0]
s0_burstcount[3:0]
s0_writedata[31:0]
s0_byteenable[3:0]
s0_readdata[31:0]
s0_waitrequest
s0_write
s0_read
s0_readdatavalid
.. 1650 .
8
359F . . E . . 81174 D7563 . . 0EFF . E 11844923 0 . 9E314 . . 7968B .
F F F F F F F
000 2 . 2B3
0 5 4
00000000 9 . . 7968B .
0 F F
Altera Corporation Avalon-MM Verilog HDL and VHDL Testbenches
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17-5 Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves