Altera Avalon Verification IP Suite - Manual (Page 44)

set_command_request()
void set_command_request(Request_t request)
Prototype:
Verilog HDL: Request_t request
VHDL: Request_t request , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the transaction type to read or write in the command descriptor. The
enumeration type defines
REQ_READ = 0 and REQ_WRITE = 1.
Description:
Verilog HDL, VHDL Language support:
set_command_timeout()
void set_command_timeout(int cycles)
Prototype:
Verilog HDL: int cycles
VHDL:
int cycles
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the number of elapsed cycles between waiting for a
waitrequest
and when
time out is asserted. Disables time-out by setting the value to 0.
Description:
Verilog HDL, VHDL Language support:
set_command_transaction_id()
void set_command_transaction_id(bit[AV_TRANSACTIONID_W-1:0] id)
Prototype:
AvalonTransactionId_t id.
Verilog HDL:
tid
VHDL:
tid
,
bfm_id
,
req_if(bfm_id)
Arguments:
void
Returns:
Sets the transaction id number in the command descriptor. Description:
Verilog HDL, VHDL Language support:
Avalon-MM Master BFM Altera Corporation
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set_command_request() 5-22