Altera Avalon Verification IP Suite - Manual (Page 27)

Description Symbol
Signals when write and read commands are presented on the interface. The event name is
signal_command_issued
.
S
ci_1
–S
ci_2
Signals the first read response. The event name is signal_response_complete. S
rc_1
Signals the end of the test. The event name is
signal_all_transactions_complete.
S
atc
Block Diagram
The following figure provides a block diagram of the Avalon-MM Master BFM. As this figure illustrates,
the BFM includes the following major blocks:
• Avalon-MM Master API—Provides methods to create Avalon-MM transactions and query the state of
all queues.
• Command Descriptor—Accumulates the fields of an Avalon-MM command transaction using the
set_command
API call. Inserts completed commands onto the pending command queue.
• Avalon-MM Interface Driver—Issues transfers to the system interconnect fabric and holds each transfer
until waitrequest is deasserted. For burst transfers, there is a separate transfer for each word of the
burst. The system interconnect fabric can assert
waitrequest
for each word of the burst, as necessary.
• Timestamp Counter—Records a timestamp with commands for use in timing calculations. The driver
and monitor both use the timestamp counter for timing calculations.
• Avalon-MM Interface Monitor—Monitors the system interconnect fabric and records responses for read
transfers in the response queue.
• Response Descriptor—Collects information about completed transactions using the
get_response_
API calls. The testbench uses this information for further analysis.
Altera Corporation Avalon-MM Master BFM
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5-5 Block Diagram