Altera Avalon Verification IP Suite - Manual (Page 136)

signal_sink_ready_deassert
signal_sink_ready_deassert
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that
sink_ready
is deasserted, turning on back pressure. Description:
Verilog HDL Language support:
signal_transaction_received
signal_transaction_received
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that the transaction has been received and queued. Description:
Verilog HDL Language support:
Avalon-ST Sink BFM Altera Corporation
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