Altera Avalon Verification IP Suite - Manual (Page 190)

signal_max_result_queue_size
signal_max_result_queue_size Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the maximum pending result queue size threshold has been exceeded. Description:
Verilog HDL Language support:
signal_min_instruction_queue_size
signal_min_instruction_queue_size Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the pending instruction queue size is below the minimum threshold. Description:
Verilog HDL Language support:
signal_min_result_queue_size
signal_min_result_queue_size
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the pending result queue size is below the minimum threshold. Description:
Verilog HDL Language support:
signal_result_received
signal_result_received
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that a result has been received. Description:
Verilog HDL Language support:
Altera Corporation Nios II Custom Instruction Master BFM
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14-15 signal_max_result_queue_size