Altera Avalon Verification IP Suite - Manual (Page 199)

retrieve_instruction()
void retrieve_instruction
. Prototype:
VHDL:
output ci_data_t dataa
Verilog HDL:
output ci_data_t dataa
Arguments:
output ci_data_t datab output ci_data_t datab
output ci_n_t n output ci_n_t n
output ci_addr_t a output ci_addr_t a
output ci_addr_t b output ci_addr_t b
output ci_addr_t c output ci_addr_t c
output logic readra output logic readra
output logic readrb output logic readrb
output logic writerc output logic writerc
output ci_data_t idle output ci_data_t idle
bfm_id
req_if(bfm_id)
void Returns:
A simplified API to retrieve instruction. Description:
Verilog HDL, VHDL Language support:
set_clock_enable_timeout()
void set_clock_enable_timeout()
Prototype:
Verilog HDL:
int timeout
VHDL:
int timeout
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the timeout value for the clock enable. Set the value to
0
to disable timeout. Description:
Verilog HDL, VHDL Language support:
Altera Corporation Nios II Custom Instruction Slave BFM
Send Feedback
15-9 retrieve_instruction()