Altera Avalon Verification IP Suite - Manual (Page 46)

set_response_timeout()
void set_response_timeout(int cycles)
Prototype:
Verilog HDL: int cycles
VHDL: int cycles , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the number of cycles that may elapse before response time out. Disable time-
out by setting the value to 0. Description:
Verilog HDL, VHDL Language support:
signal_all_transactions_complete
signal_all_transactions_complete
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that all queued transactions have completed. Description:
Verilog HDL Language support:
signal_command_issued
signal_command_issued
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that the currently pending command has been driven to the interface. Description:
Verilog HDL Language support:
Avalon-MM Master BFM Altera Corporation
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set_response_timeout() 5-24