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Signal_command_received, Signal_fatal_error, Signal_read_response_complete – Altera Avalon Verification IP Suite User Manual

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signal_command_received

signal_command_received

Prototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

void

Returns:

Notifies the testbench that a command was detected on the Avalon port.
When this event is received, the testbench responds with a

set_interface_

wait_time

call. This call dynamically backpressures the driving Avalon

master.

Description:

Verilog HDL

Language support:

signal_fatal_error

signal_fatal_error

Prototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

void

Returns:

Notifies the testbench that a fatal error has occured in this module.

Description:

Verilog HDL

Language support:

signal_read_response_complete

signal_read_response_complete

Prototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

void

Returns:

Notifies the testbench that the read response has been received and inserted
into the response queue.

Description:

Verilog HDL

Language support:

Avalon-MM Monitor

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signal_command_received

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