Altera Avalon Verification IP Suite - Manual (Page 122)

set_response_timeout()
set_response_timeout(int cycles)
Prototype:
Verilog HDL: cycles
VHDL: cycles , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the number of cycles that have to elapse before a response timeout is asserted.
Disable the time-out by setting the cycles argument to zero. Description:
Verilog HDL, VHDL Language support:
set_transaction_channel()
set_transaction_channel(STChannel_t channel)
Prototype:
Verilog HDL: channel
VHDL:
channel
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the channel identifier in the out-going transaction. Description:
Verilog HDL, VHDL Language support:
set_transaction_data()
set_transaction_data(STData_t data)
Prototype:
Verilog HDL:
data
VHDL:
data
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the value of data in the out-going transaction. Description:
Verilog HDL, VHDL Language support:
Avalon-ST Source BFM Altera Corporation
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set_response_timeout() 8-10