Get_ci_clk_en(), Get_instruction_a(), Get_instruction_b() – Altera Avalon Verification IP Suite User Manual
Page 195: Get_instruction_c(), Get_ci_clk_en() -5, Get_instruction_a() -5, Get_instruction_b() -5, Get_instruction_c() -5

get_ci_clk_en()
void get_ci_clk_en(bit enable)
Prototype:
Verilog HDL: None
VHDL:
clk_en
,
bfm_id
,
req_if(bfm_id)
Arguments:
bit enable
Returns:
Retrieves the clock enable signal.
Description:
Verilog HDL, VHDL
Language support:
get_instruction_a()
string get_instruction_a()
Prototype:
Verilog HDL: None
VHDL:
instruction_a
,
bfm_id
,
req_if(bfm_id)
Arguments:
ci_addr_t
Returns:
Retrieves the instruction register file address
a
value.
Description:
Verilog HDL, VHDL
Language support:
get_instruction_b()
string get_instruction_b()
Prototype:
Verilog HDL: None
VHDL:
instruction_b
,
bfm_id
,
req_if(bfm_id)
Arguments:
ci_addr_t
Returns:
Retrieves the instruction register file address
b
value.
Description:
Verilog HDL, VHDL
Language support:
get_instruction_c()
string get_instruction_c()
Prototype:
Verilog HDL: None
VHDL:
instruction_c
,
bfm_id
,
req_if(bfm_id)
Arguments:
ci_addr_t
Returns:
Retrieves the instruction register file address
c
value.
Description:
Verilog HDL, VHDL
Language support:
Altera Corporation
Nios II Custom Instruction Slave BFM
15-5
get_ci_clk_en()