Altera Avalon Verification IP Suite User Manual
Page 217
The Master Command Thread performs the following functions:
• Generates random commands
• Passes the commands to Avalon-MM Master BFM
• Saves the commands in a FIFO for command and response verification
• For read commands, the master waits for a valid response and verifies it against the expected read data.
The Slave Thread performs the following functions:
• Randomly sets backpressure cycles to Avalon-MM Slave BFM
• Waits for valid commands
• Retrieves valid commands from the Avalon-MM Slave BFM
• Verifies commands against the expected command
• Sends read data for read commands. The read data is saved in a FIFO for verification
The test program sends the following transaction types:
• Non-bursting writes
• Non-bursting reads
• Bursting writes
• Bursting reads
Running the Testbench for a Single Avalon-MM Master and Slave Pair
1. Unzip
ug_avalon_verification.zip
to a working directory.
2. Open
.
3. Complete the following steps to generate the testbench:
a. On the Generate menu, select Generate HDL.
b. Specify the parameters shown in the following table:
Table 17-3: Generation Parameters
Value
Parameter
Synthesis
Leave this option off
Create HDL design files for synthesis
Leave this option off
Create timing and resource estimates for third-party
EDA synthesis tools
Leave this option on
Create block symbol file (.bsf)
Simulation
VHDL
Create simulation model
Leave this option off
Allow mixed-language simulation
Output Directory
Path
c. Click Generate.
Altera Corporation
Avalon-MM Verilog HDL and VHDL Testbenches
17-7
Running the Testbench for a Single Avalon-MM Master and Slave Pair